Electrotechnology - Electronic Technology - APS

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1. Semiconductor

1.1 Type

  • Intrinsic semiconductor

    • Si,silicon

    • charge carrier : electrons & electron hole

    • carrier too less

  • extrinsic semiconductor

    • N : add P phosphorus

      • electrons more

    • P : add B boron

      • holes more

1.2 PN Junction

  • Forward bias : with current
  • Reverse bias : approximal no current

1.3 Diodes

  • forward voltage : Si 0.7
  • reverse voltage

  • use for protect, regulate voltage

1.3.1 Zener diode

1.3.2 LED

1.3.3 Photodiode

1.4 Transistor

  • PNP
  • NPN
  • base
  • collector
  • emitter

1.4.1 Principles

$\beta=\dfrac{I_{ce}}{I_{be}}$

1.4.2 Properties

  • Dead V :
    • Si : 0.5
    • Ge : 0.1
  • $U_{BE}$
    • NPN Si 0.7V
    • PNP Ge -0.3V

  • Ib<0

    • none work
  • Ib>0, Ube>0.5

    • linear area
    • $I_C=\beta I_B$
    • $U_{BE}=0.7V$
  • Ib>0,Ube<0.5

    • $U_{BE}=0.7V$
    • $U_{CE}=0.3V$

1.4.3 Parameters to work right

  • $I_{CM}$ : or $\beta$ decrease, still work
  • $U_{CEO}$ : maximum between c/e

2 Amplifying circuit

2.1 Common emitter amplifying circuit

Superposition Principle

2.2 Static analysis

2.3 Dynamic Analysis

2.3.1 Calculation

  • $r_{be}=200+(1+\beta)\dfrac{26(\rm mV)}{I_E(m\rm mA)}\Omega$
  • $I_E$ : emitter static value
  • Gain : $A_u=-\beta\dfrac{R_C}{r_{be}}$
  • Big input R : $R_B\/\/r_{be}$
  • Small output R : $R_C$

2.3.2 Draw

  • Q too high$\rightarrow$Saturation distortion

  • Q too low$\rightarrow$Cutoff distortion

2.4 Voltage divider bias circuit

$R_E$ stabilize $I_C$

$C_E$ stabilize Q

2.5 Common collector amplifier circuit

2.6 Differential amplifier circuit

Zero drift, 2 direct connect

2.7 MOSFET

metal-oxide-semiconductor field-effect transistor

  • Source
  • Gate
  • Drain

3. Operational Amplifier

CF741

3.1 Application

  • Positive-feedback applications

  • Negative-feedback applications : inverting amplifier

3.2 Add and Minus

Superposition Principle

  • Add

  • Minus

4. Feedback

Output connect with Input

Type

  • local feedback
  • Interstage feedback

  • AC feedback
    • negative : decrease amplify factor, increase other like factor stable
  • DC feedback : stabilize Q

  • series : compare with voltage
  • parallel : compare with current

  • voltage : stable output v, decrease input R
  • current : stable output i, increase output R
  • Negative feedback direct judgement

5 DC regulated power supply

5.1 Rectifier circuit

  • Single-phase half-wave rectifier circuit

    • $U_O=\dfrac{\sqrt2}{\pi}U=0.45U$
    • $I_D=I_O=0.45\dfrac{U}{R}$
    • $U_{RM}=\sqrt2U$
  • Single-phase full-wave rectifier circuit

    • $U_O=\dfrac{2\sqrt2}{\pi}U=0.9U$
    • $I_O=0.9\dfrac{U}{R}\I_D=\dfrac{I_O}{2}$
    • $U_{RM}=2\sqrt2U$
  • Single-phase bridge rectifier circuit

    • $U_O=\dfrac{2\sqrt2}{\pi}U=0.9U$
    • $I_O=0.9\dfrac{U}{R}\I_D=\dfrac{I_O}{2}$
    • $U_{RM}=\sqrt2U$

5.2 RC Filter

choose $\tau=RC\ge(3\sim5)\dfrac{T}{2}$

5.3 Regulator circuit

use zener diodes

5.4 3 Terminal Voltage Regulator

  • W7805 (W78XX)

  • W117

6. Gate circuit

6.1 Signal

  • analog signal

  • digital signal

    • rectangular signal
    • apex signal

6.2 Logic gate

  • and : Y=ABC
  • or : Y=A+B+C
  • not : $Y=\bar A$

Combination

  • nand : $Y=\overline{ABC}$
  • nor : $Y=\overline{A+B+C}$

6.3 TTL Gate Circuit

$Y=\overline{AB}$

  • 74LS20 4in2gate
  • 74LS00 2in4gate

6.4 Tri-state gate

6.5 Logical algebra

6.6 Logical function

$$Y=(A,B,C\cdots)$$

  • logic formula

  • logic state table

  • logic graph - carnot graph

  • simplify

6.7 Design

  1. Logic abstract
  2. Logic state table
  3. formula
  4. graph

6.8 Adder

6.7 Encoder & Decoder

  • 8line-3line encoder 3line-8line74LS138

  • 8421 decoder

  • 74LS147 binary$\rightarrow$decimal

7. Multivibrator

7.1 Bistablemultivibrator

7.1.1 RS

  • type1 [$\rm \overline{SR}$ NAND latch]

  • type2 [SR NOR latch]

  • controllable [Gated SR latch]

7.1.2 JK

2 controllable RS

1 question : 1 change in CP=1

  • if $Q_{n-1}=0$ : S=J, R=0,$Q_n=1/Q_n=Q_{n-1}$
  • if $Q_{n-1}=0$ : S=J, R=0,$Q_n=1/Q_n=Q_{n-1}$

7.1.3 D

7.1.4 T

T=1, T’ latch

7.2 Register

temporarily save data

  • digital r

    • parallel input
    • parallel output

  • shift r

    • serial input
    • parallel output

7.3 Counter

7.3.1 Binary

7.3.2 Decimal

7.3.3 74LS290

binary quinary decimal

any

7.4 555